The invention generally relates to oxide-containing materials, along with articles of manufacture comprising the same, and methods of forming the same.
As device dimensions are scaled according to the 1999 Technology Roadmap for Semiconductors, 1999 Edition (http://public.itrs.net), the equivalent gate oxide thickness, EOT, should decrease below about 1.5 nm. At this silicon dioxide (SiO2) thickness, the direct tunneling current for a one volt potential drop across the oxide is typically greater than 1 A/cmxe2x88x922. Such a volt potential drop is potentially disadvantageous in that it begins to reduce the ratio of on- to off-state current in a field effect transistor. In order to attempt to reduce the off-state leakage currents due to tunneling through SiO2 and maintain a capacitance that is equivalent to that obtained with a SiO2 dielectric with a physical thickness of 1.5 nm and below, alternative high-k dielectrics are being investigated. See e.g., J. Robertson, J. Vac. Sci. Technol. B 18(3) (2000) and G. D Wilk, et al., J. Appl. Phys. 89, 5243 (2001). These high-k alternative dielectrics are potentially capable of providing the required levels of EOT for device scaling at larger physical thickness. Thus, a pathway for the potential reduction of tunneling current is provided. Other factors such as conduction band offset energies also are believed to play a role in influencing tunnel leakage, and these offset energies generally decrease with increasing k.
Recently, aluminum oxide has been the focus of several studies. Klein et al. Appl. Phys. Lett. 75, 4001 (1999) propose the deposition of aluminum oxide with a CVD growth method. This reference proposes a silicate layer being present at the interface on aluminum oxide and silicon, as measured by nuclear resonance profiling (NRP) and X-ray photoelectron spectroscopy (XPS). Gusev et al. Appl. Phys. Lett. 76, 176 (2000) propose atomic layer CVD (ALCVD) where they investigated both the physical and electrical properties of an aluminum oxide layer. Gusev et al. propose that it is possible to deposit aluminum oxide on hydrogen-terminated silicon without forming an interfacial layer using NRP, medium energy ion scattering (MEIS), and high-resolution transmission electron microscopy (TEM).
Transistors with an equivalent gate oxide thickness of 0.96 nm with aluminum oxide as the material are proposed by Chin et al. Tech. Dig. VLSI Symp, 16 (2000). Chin et al. proposes that these devices have a Dit value greater than or equal to 310 cmxe2x88x922 and a positive flat band shift, indicating a negative fixed charge. Buchanan et al., Tech. Dig. Intl. Electron Devices Meet, 223 (2000) propose an nMOSFET formed by ALCVD Al2O3 with 0.08 xcexcm gate lengths. This reference also proposes a negative fixed charge for devices with an equivalent oxide thickness of 1.3 nm.
Notwithstanding the above, there remains a need in the art for oxide materials that may be used in semiconductor devices which have the potential to reduce direct tunneling current in the devices.
The present invention addresses the inadequacies of the prior art. In one aspect, the invention provides a non-crystalline oxide represented by the formula (I):
xe2x80x94(ABO4)x(MnOm)1xe2x88x92xxe2x80x94xe2x80x83xe2x80x83(I) 
wherein:
A is an element selected from Group IIIA of the periodic table;
B is an element selected from Group VB of the periodic table;
O is oxygen;
M is an element selected from either Group IIIB or Group IVB of the periodic table; and
n ranges from about 0.5 to about 2.5, m ranges from about 1.5 to about 3.5, and x is a fraction ranging from 0 to 1.
In another aspect, the invention provides a a non-crystalline oxide represented by the formula (II):
xe2x80x94(AlO2)j(MnOm)kxe2x80x94xe2x80x83xe2x80x83(II) 
wherein:
Al is aluminum;
O is oxygen;
M is an element selected from either Group IIIB or Group IVB of the periodic table; and
j ranges from about 0.5 to about 4.5; k is equal to about 1; n ranges from about 0.5 to about 2.5, and m ranges from about 1.5 to about 3.5.
In another aspect, the invention provides methods of forming a non-crystalline oxide represented by the formulas (I) and (II) as described in greater detail hereinbelow.
In another aspect, the invention provides a field effect transistor. The field effect transistor comprises an integrated circuit substrate having a first surface, source and drain regions in the substrate at the first surface in a spaced apart relationship, and a gate insulating layer on the substrate at the first surface between the spaced apart source and drain regions. The gate insulating layer comprises any of the non-crystalline oxides represented by formulas (I) or (II) described hereinbelow.
These and other aspects and advantages of the present invention are set forth hereinbelow.